Quiz Electronics Engineering 24 March 2020

Quiz Electronics Engineering

Exam: NIC

Topic: Miscellaneous

Date: 24 March, 2020

 

Each Question carries 1 Mark

Negative Marking:  1/4

Time: 10 Minutes

 

Q1. A compiler which allows only the modified section of the source code to be recompiled is called as

(a)Re-configurable compiler

(b)Dynamic compiler

(c)Subjective compiler

(d)Incremental compiler

L1 Difficulty 4

QTags Compiler Design

QCreator Vikram Kumar

 

Q2. If user participation is available, which model is to be chosen?

(a)RAD model

(b)Waterfall model

(c)Iterative enhancement model

(d)Spiral model

L1 Difficulty 4

QTags Software Engineering

QCreator Vikram Kumar

 

Q3. Revoke is a command of which language of DBMS?

(a)DML (Data Manipulation Language)

(b)DCL (Data Control Language)

(c)DDL (Data Definition Language)

(d)TCL (Transaction Control Language)

L1 Difficulty 3

QTags DBMS

QCreator Vikram Kumar

 

Q4. In an Entity-Relationship (E-R) diagram weak entity is represented by which of the following?

(a)Double ellipse

(b)Dashed ellipse

(c)Double rectangle

(d)Rectangle

L1 Difficulty 3

QTags DBMS

QCreator Vikram Kumar

 

Q5.The dual-port version of DRAM formally used in graphics adaptors is :

(a)VRAM

(b)FPM DRAM

(c)EDORAM

(d)DDRSDRAM

L1 Difficulty 4

QTags Digital Electronics

QCreator Vikram Kumar

 

Q6. The topology with highest reliability:

(a)bus topology

(b)star topology

(c)ring topology

(d)mesh topology

L1 Difficulty 2

QTags Networking

QCreator Vikram Kumar

 

Q7. Which of the following modulations is non-linear?

(a)AM

(b)SSB

(c)FM

(d)none of these

L1 Difficulty 3

QTags Communication Engineering

QCreator Vikram Kumar

 

Q8. What is the frequency of the ac waveform V = 10.8 sin 50t

(a)96 Hz

(b)96 Hz

(c)96 Hz

(d)None of these

L1 Difficulty 2

QTags Network & Circuit Theory

QCreator Vikram Kumar

 

Q9. For trigging the thyristor it requires

(a)only a pulse

(b)Continuous plus of current

(c)Both (a) and (b)

(d)None of the above

L1 Difficulty 3

QTags Power electronics (electrical engineering)

QCreator Vikram Kumar

 

Q10. Number of address lines required to address 8 k byte of memory is

(a)16

(b)14

(c)15

(d)13

L1 Difficulty 2

QTags Computer Organization & Microprocessor

QCreator Vikram Kumar

 

 

SOLUTIONS

 

S1. Ans.(d)

Sol:

  • An Incremental compiler is a kind of incremental computation applied to the field of compilation. An ordinary compiler builds all program modules but incremental compiler recompiles only those portions of a program that have been modified.
  • Reconfigurable computing, a computer architecture, combines the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics like field-programmable gate arrays (FPGAs). The reconfigurable computations is performed by configuring the fabric to implement a circuit customized for each particular reconfigurable computation. The compiler does computations in a single static configuration rather than following an instruction sequence, reducing instruction bandwidth and control overhead.
  • Dynamic compilation is used to gain performance during program execution. The machine code emitted by a dynamic compiler is constructed and optimized at program runtime. So, the use of dynamic compilation enables optimizations for efficiency which is not available to compiled programs except through code duplication or metaprogramming.

 

S2. Ans.(a)

Sol:

  • In Waterfall Model the project activities are breakdown into linear sequential phases. Here, each phase consists of series of tasks with different objectives. In this model development of one phase starts only when the previous phase is complete. The phases of this model are- Conception, Initiation, Analysis, Design, Construct, Testing, Production/Implementation and Maintenance. It is a sequential model. It is used for small projects.
  • Spiral Model is the combination of Iterative development model and sequential linear development model. It provides support for risk handling. It has four phases:- Planning, design, Construct and Evaluation. It is used for large projects.
  • The Iterative enhancement model is also called incremental model. It comprises the features of waterfall model in an iterative manner. The incremental model has phases similar to the linear sequential model but has an iterative nature of prototyping. In the implementation phase, the project is divided into small subsets called increments that are implemented individually. In this model each phase produces an increment. These increments are identified in the beginning of the development process. The basic idea of this model is to start the process with requirements and iteratively enhance the requirements until the final software is implemented. It receives feedback from the user specifying the requirements of the software.
  • RAD model is Rapid Application Development model. It follows iterative and incremental model. In RAD model the components or functions are developed in parallel as prototypes and are integrated to make the complete product for faster product delivery. The developments are time boxed, delivered and then assembled into a working prototype. It is made sure that the prototypes developed are reusable. Active Participation of user is involved in all the four phases of RAD model.

 

S3. Ans.(b)

Sol: Revoke is a command of DCL. It is used to take back the permission or access rights of database from the users.

 

S4. Ans.(c)

Sol: Entity-Relationship (E-R) diagram displays the relationships of entity set i.e. logical structure of databases, stored in a database.

  • Rectangle: represents Strong entity set
  • Double Rectangle: represents Weak entity set.
  • Diamonds: represents relationship.
  • Lines: links attributes to entity and entity with other relationship.
  • Double Ellipse: depicts Multivalued attributes.
  • Dashed Ellipse: depicts Derived attributes.

 

S5.Ans.(a)

Sol:

  • FPM DRAM is the acronym of Fast Page Mode Dynamic Random Access Memory. Due to the fast page access it has a higher performance than the conventional DRAM. FPM-DRAM controller keeps RAS in the lower state to get rid of the retransmission of the row number.
  • Extended Data Out Random Access Memory (EDO RAM) is a DRAM chip. It was designed to improve the performance of FPM DRAM used in the 90’s. Its main feature was that it eliminates the wait time by fetching the next block of memory at the same time that it sends previous block to the CPU. This allows a degree of pipelining which improves performance.
  • Video RAM, or VRAM, is a dual-ported variant of dynamic RAM (DRAM). VRAM is a buffer between the computer processor and the display, also called as frame buffer. It is stored in some graphics adapters.
  • DDR SDRAM is the acronym of double data rate synchronous DRAM. DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. It activates output on both the rising and falling edge of the system clock rather than on just the rising edge, results in doubling output.

 

S6. Ans.(d)

Sol: Mesh topology routes data sent through any of several possible nodes to the receiving node. It is expensive for setup as it connects every node to all nodes on the network. However, it is considered the most reliable because it is most redundant of all topology i.e. if one node fails, the network can route traffic to another node.

 

S7. Ans.(c)

Sol: FM is non-linear.

 

S8. Ans.(b)

Sol:

We know,        ω = 2πf

⟹                  ω = 50

⟹                   2πf = 50

So,                    = 7.96 Hz

 

S9. Ans.(a)

Sol: For turning Thyristor “ON” we need to inject a small trigger pulse of current (not a continuous current) into the Gate terminal when the thyristor is in its forward direction. Thyristor is brought from forward blocking mode to forward conduction mode by turning it on by exceeding the forward break over voltage or by applying a gate pulse between gate and cathode.

 

S10. Ans.(d)

Sol:

8 K byte = 8 x 1024

= 2³ x 210  =  213

So, 13 no. of address lines are required.

 

 

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