Quiz Electronics Engineering 2 June 2020

Quiz Electronics Engineering
Exam: NIC
Topic: Miscellaneous
Date: 02/06/2020

Each Question carries 1 Mark
Negative Marking: 1/4
Time: 10 Minutes

Q1. A class member declared protected in Java becomes member of subclass of which type?
(a) Public Member
(b) Protected Member
(c) Private Member
(d) Static Member

Q2. How many full adders are required to construct an m-bit parallel adder?
(a) m
(b) m – 1
(c) m/2
(d) m + 1

Q3. Which type of traversal of binary search tree outputs the value in sorted order?
(a) Pre-order
(b) In-order
(c) Post-order
(d) Level-order

Q4. A positive AND gate is also a negative
(a) NAND gate
(b) OR gate
(c) AND gate
(d) NOR gate

Q5. Events A and B are mutually exclusive and have non-zero probability. Which of the following statement is TRUE?
(a) P(AUB) = P(A) + P(B)
(b) P(B’) > P(A)
(c) P(A∩B) = P(A)P(B)
(d) P(B’) < P(A)

Q6. Assume transaction A holds a shared lock R. If transaction B also requests for a shared lock on R. It will
(a) result in deadlock situation
(b) immediately be granted
(c) immediately be rejected.
(d) None of the above

Q7. Web links are stored within the page itself and when you wish to jump to the page that is linked, we select the hotspot or anchor. This technique is called
(a) Hypertext
(b) Hypermedia
(c) both (a) & (b)
(d) Anchoring

Q8. Which of the following is not a form of main memory?
(a) Instruction opcode
(b) Instruction register
(c) Instruction cache
(d) Translation look-aside buffer

Q9. The number of the edges in a regular graph of degree ‘d’ and ‘n’ vertices is
(a) Maximum of n, d
(b) n + d
(c) nd
(d) nd/2

Q10. Synthesized attribute can easily be simulated by an
(a) LL grammar
(b) ambiguous grammar
(c) LR grammar
(d) None of the above




S1. Ans.(c)
Sol. A class member which is declared protected from before becomes the Private member of subclass.

S2. Ans.(a)
Sol. For n-bit adder, we require-
(a) (n-1) FA and 1 HA ; or
(b) n FA ; or
(c) (2n-1) HA & (n-1) OR gate.

S3. Ans.(d)
(a) In Pre-order , the Root node is visited first, then the Left subtree and at last Right Subtree.
(b) In-order, Left Subtree is visited first , then the Root node, and at last Right Subtree.
(c) Post-order, at first Left Subtree, then Right Subtree and finally Root node.
(d) Level-order is breadth first traversal for the tree.

S4. Ans.(b)
Sol. Positive AND gate has input A, B and output AB.
Negative OR gate will have inverter at both inputs and 1 Output.
So, Output at the negative OR gate is
(A ̅+B ̅ ) ̅ = (AB) ̅ ̅ = AB = Positive AND gate output

S5. Ans.(a)
Sol. By principle of inclusion and exclusion, we get
P(AUB) = P(A) + P(B) + P(A∩B)
In Mutually exclusive condition –
P(A∩B) = 0

So, P(AUB) = P(A) + P(B)

S6. Ans.(b)

immediately be granted

S7. Ans.(c)

Sol. Both (a) and (b)

S8. Ans.(a)
Sol. Instruction opcode tells about what operation to be performed. Excluding it, all are form of a main memory.

S9. Ans.(d)
Sol. Given:
Number of vertices = n
Degree of each vertices or number of neighbours of each vertices = d
So, Total edges = nd/2

S10. Ans.(c)
Sol. Both Synthesized attribute and LR grammar are evaluated in bottom up method. So, these can be simulated easily.

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