Quiz Electronics Engineering 18 Sep 2020

Quiz Electronics Engineering
Exam: NIC
Topic: Miscellaneous
Date: 18/09/2020

Each Question carries 1 Mark
Negative Marking: 1/4
Time: 10 Minutes

Q1. The number of layers in ISO OSI reference model is
(a) 5
(b) 6
(c) 7
(d) None of these

Q2. A capacitor opposes
(a) Change in voltage
(b) Change in current
(c) Both change in voltage and current
(d) None of these

Q3. In a discrete-time Low Pass Filter, the frequency response is
(a) a periodic
(b) a periodic with response restricted to (〖-ω〗_c to +ω_c)
(c) periodic with period 2π.
(d) Quasi periodic with response extending to infinity

Q4. 8085 Microprocessor does not have:
(a) Over Flag
(b) Parity Flag
(c) Zero Flag
(d) Auxiliary Carry Flag

Q5. TCP/IP model does not have ______ layer but OSI model have this layer.
(a) network layer
(b) transport layer
(c) application layer
(d) session layer

Q6. Which of the following device has characteristic close to that of an ideal voltage source?
(a) Crystal diode
(b) Vacuum diode
(c) Zener diode
(d) All of the above

Q7. A deterministic signal has power spectrum given in figure. The minimum sampling rate needed to completely represent signal is

(a) 1 kHz
(b) 4 kHz
(c) 3 kHz
(d) 4 Hz

Q8. Which statement is correct:
(a) HLDA signal generated by DMA controller
(b) HLDA signal generated by DMA controller for 8085
(c) HOLD signal is generated by 8085 for DMA controller
(d) HLDA signal is generated by 8085 for DMA controller

Q9. Assertion(A): A Look-Ahead Carry adder is a fast adder.
Reason(R): A Parallel Carry Adder generates sum digits from the input digits.
(a) Both A and R are True and R is the correct explanation of A.
(b) Both A and R are True but R is not the correct explanation of A.
(c) A is True but R is False.
(d)A is False but R is True.

Q10. The flux and potential functions due to a line charge and due to two concentric circular conductors are of the following form:
(a) Concentric circular equipotential lines and straight radial flux lines.
(b) Concentric circular flux lines and straight equipotential lines
(c) equipotential due to line charge are concentric cylinders and equipotential due to two conductors are straight lines.
(d) Equipotential due to line charge are straight flat surfaces and those due to two conductors are concentric cylinders.

SOLUTIONS

S1. Ans.(c)
Sol. There are 7 layers in the OSI(Open System Interconnection) model. Those are – Application Layer, Presentation Layer, Session Layer, Transport Layer, Network Layer, Data Link Layer and Physical Layer.

S2. Ans.(a)
Sol. If capacitors supports sudden change in voltage then it requires large amount of current which is tending to infinity to flow through low impedance capacitor. This infinity current is not possible. Hence, Capacitor opposes sudden change in voltage.

S3. Ans.(c)
Sol. Sampling in one domain leads to periodicity in other domain.

S4. Ans.(a)
Sol. There are 5 flags in the flag register of 8085 microprocessor. Each flag is a 1-bit flip-flop which holds the status of the accumulator after execution of any instruction.

S5. Ans.(d)
Sol. In OSI model, there are three layers which are not present in TCP/IP model. Those are Presentation and Session layer.
Application, Presentation and Session Layer are combined as Application Layer in TCP/IP.
Data Link Layer and Physical Layer is combined as Network Access Layer.

S6. Ans.(c)
Sol. Ideal voltage source has internal resistance zero so voltage remains constant w.r.t change in current. A Zener diode, when reversed biased acts as a constant voltage source. So, its characteristics matches to that of ideal voltage source.

S7. Ans.(b)
Sol. Given:
fmax = 2 kHz
We know that, minimum sampling rate is
(fs)min = 2 fmax = 2 x 2 kHz = 4kHz
Therefore, Minimum sampling rate is 4kHz.

S8. Ans.(d)
Sol. ‘HLDA’ is a Hold Acknowledgement signal generated by 8085 microprocessor for DMA controller. It gives signal to allow direct access of the memory.
HOLD signal is generated by DMA controller and when it is ‘HIGH’ then it instructs processor that another master is calling for this line.

S9. Ans.(a)

S10. Ans.(c)

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